i need some help please in verilog
i have to build an automatic sequential with 74613 counter and 32x4 Prom memory which has the evolution
of the following states (shown in the figure attched to this message).
#-Link-Snipped-#
![[IMG]](proxy.php?image=http%3A%2F%2Fwww.fileden.com%2Ffiles%2F2009%2F3%2F11%2F2359256%2Fproblem.JPG&hash=2b61e4675c9b27dafd454584cc8febb3)
i don t know where to start, any help, advice would be greatly appreciated.
Thank you.
of the following states (shown in the figure attched to this message).
#-Link-Snipped-#
i don t know where to start, any help, advice would be greatly appreciated.
Thank you.
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