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# Difference Between Latches & Flip Flops?

Question asked by Kaustubh Katdare in #Coffee Room on Mar 25, 2011
Kaustubh Katdare 路 Mar 25, 2011
Rank A1 - PRO
As part of our group study initiatives, here's a topic suggested by Cranky Here: https://www.crazyengineers.com/forum...oup-study-digital-rc-circuits.html#post153389

Discuss the topic in this thread and build up a discussion on the topic. 😀 All the best! Posted in: #Coffee Room
silverscorpion 路 Mar 26, 2011
Rank A3 - PRO
Well, both latches and flip-flops are circuits whose output depends on the inputs and the previous outputs..

But the difference is that, a flip-flop will have a clock signal but a latch won't. In other words, latches are used in asynchronous circuits and flip-flops in synchronous circuits.

So, a flip-flop is nothing but a clocked latch! 馃榾
The Redeemer 路 Mar 26, 2011
Rank E1 - BEGINNER
Latches are level sensitive while flip flops are edge sensitive.
cranky 路 Mar 26, 2011
Rank C3 - EXPERT
@silver scorpion,redeemer:so how does a latch work..by saying level triggered,what do we mean?Where does the value change in a latch?
The Redeemer 路 Mar 27, 2011
Rank E1 - BEGINNER
Hi Cranky,

By level sensitive we mean that output will respond to change in input as long as the control signal is high. Control signal can be a clock in case of flip flop or any other asynchronous signal in case of latch.

By edge sensitive we mean that output will only respond to input at the point when the control signal goes to high from low. Now when the control signal is high the output will not change with change in input. It will again change at the next rising edge of the clock.

cranky 路 Mar 27, 2011
Rank C3 - EXPERT
@Redeemer:So what you mean is,when it is high,the output=input?...so where does it get latched?馃槓
The Redeemer 路 Mar 27, 2011
Rank E1 - BEGINNER
@Cranky

True in case of D latch but not in other latches , take for example the SR latch. In SR latch the latching will take place when the control signal is zero and when the control signal is one the output will change according to the previous values of output and the SR value.

Control S R Q Q'
0 0 0 latch latch
0 0 1 latch latch
0 1 0 latch latch
0 1 1 latch latch
1 0 0 latch latch
1 0 1 0 1
1 1 0 1 0
1 1 1 0 0

@Moderator

Why can't I upload images from my computer?
chetan mehra 路 Mar 29, 2011
Rank D3 - MASTER
to all,
my question is:if we take a close look on the k-map simplification for the D flip flop,we see that the output does not depend on the previous outputs, but still we call it a flip flop,why?
silverscorpion 路 Mar 29, 2011
Rank A3 - PRO
Hmm.. Yeah. The output will not depend on the previous input.

In any flip flop or latch, the 'current' output will depend on the 'previous' outputs and the 'current' inputs only. Not on previous inputs..
Is it clear?
cranky 路 May 9, 2011
Rank C3 - EXPERT
@above all:thanks
Q2:How to start problems that involve designing a counter with frequency/2,f/3 etc.
Avishkar Gote 路 May 10, 2011
Rank E1 - BEGINNER
Latch is a another term used for flip-flop.Latches are level sensitive while flip flops are edge sensitive and yes both latches and flip-flops are circuits whose output depends on the inputs and the previous outputs..
Raunak1302 路 Mar 13, 2012
Rank E2 - BEGINNER
cranky
@Redeemer:So what you mean is,when it is high,the output=input?...so where does it get latched?馃槓
What do we exactly mean by getting latched??
sandeepbangalore 路 Mar 14, 2012
Rank D3 - MASTER
The example shows D-latch and D-FF.

The simplest form of data storage is latch. It's output responds immidiately to changes at the input and the input state will be remembered, or "latched" onto. While "enable" input is active the input of the latch is transparant to the output, once "enable" is disactivated the output remains locked. Flip-flops use clock as a control input. The transition on output Q occurs only at the edge of the clock pulse. Input data must present T_setup time before clock edge and remain T_hold time after.

* RESET input, while it is not shown, is present in most FF.

ex: flipflop :
module DFF (Q,_Q,D,clk,rst);
output Q,_Q;
input D,clk,rst;
reg Q,_Q;
always @(posedge clk or posedge rst)
begin
if (rst) Q <= 0;
else Q <= D;
_Q <= !Q;
end
endmodule
*****************************************************************
ex: latch :
module DLatch (Q,_Q,D,en,rst);
output Q,_Q;
input D,en,rst;
reg Q,_Q;
always @(en or D or posedge rst)
begin
if (rst) Q <= 0;
else if (en) Q <= D;
_Q <= !Q;
end
endmodule

*************************************************************
sandeepbangalore 路 Mar 14, 2012
Rank D3 - MASTER
@Raunak1302 :
Raunak1302
What do we exactly mean by getting latched??

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