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moraali

moraali

moraali is an esteemed member of CrazyEngineers since May 27, 2009

Posts contributed
10
Birthday
N/A
Jun 1, 2009
Good morning, Thank you sir for your reply. I will try. But do you have any Auto_Baud in vhd? I am not expert in Verilog. Need to learn , and...
Jun 1, 2009
Good evening, Thank you for replying . When you said " Your FPGA doesn't seem to be generating any handshaking signals (atleast according to the schematic, the handshaking signals are...
May 31, 2009
Good evening, I am a bit confuse 1) "Your FPGA doesn't seem to be generating any handshaking signals (atleast according to the schematic, the handshaking signals are looped). " That...
May 31, 2009
Good evening, Thank you for your previous reply. I am not sure what this mean clearly " Your FPGA doesn't seem to be generating any handshaking signals (atleast according to...
May 31, 2009
Good morning Mr Debu, Thank you for your reply. Really appreciate your guide.I am not from engineering , so if my question is annoying , please forgive me. I am...
May 31, 2009
Good morning, Thank you very much for your reply. Really appreciate it. I want to send you some pictures. How can I send to you, becasue I can not find...
May 30, 2009
Good evening, Based on above, I like to show the cable connection. I am not sure whether it should be null modem or not. If it should , please let...
May 30, 2009
Good evening, Thank you for replying. I am not from engineering background. 1) May I know what should I do to solve the first question? 2) And for the 2nd...
May 28, 2009
Good morning, Before I start, I would like to thank you for replying. My problem is simple, but (because I am not from enginnering background) I am not sure how...
May 27, 2009
Good morning, My name is Moraali. I am currently doing a project, but I have a problem on the cable communication issue for more than 6 months. FPGA is a...
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    moraali joined CrazyEngineers on May 27, 2009

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