Complicated Xilinx FPGA problem

@moraali-tVW4Wl • Oct 25, 2024

Oct 25, 2024

2.2K

Good morning,
My name is Moraali. I am currently doing a project, but I have a problem on the cable communication issue for more than 6 months.
FPGA is a Xilinx chip... You can get the info from #-Link-Snipped-#
I am using Virtex4 ML401 (LX type)
The data sheet is on (look on the top left at sheet 12 )
#-Link-Snipped-#
================================================
Description
So by using DMM, I found out that the PC and the Modem port is not loopback. Only the FPGA is loopback (pin 1,4and 6 is connected).
PC => Male Port
Modem => Female Port
FPGA => Male Port
I tested the cables (NOT the PC , NOT the MODEM , NOT the FPGA .... ONLY FROM THE CABLES USED) for three times and the result is below (for 9 Pin D Type ) :-
1) Presently what cable you are using in between PC and Modem? For your info, the flow control is none
WORK FINE
PC Modem
2 => 2
3 => 3
5 => 5

2) And also what cable in between FPGA and PC?
WORK FINE
PC FPGA
2 => 3
3 => 2
5 => 5

3) I just tested between FPGA and Modem
DOES NOT WORK FINE
FPGA Modem
2 => 2
3 => 3
5 => 5

I am not from engineering background. So, I am not so sure about labeling the Tx and Rx. I just assume that from the PC the 2 is Rx and the 3 is Tx. And 5 is definitely Gnd
a)Whether using any Hardware handshaking in between PC and Modem? - On both the 9 Pin D Type Connector check out the Pins
1- DCD
4 - DTR
6 - DSR
7 - RTS
8 - CTS
PC (Female) Modem (Male)
1 => 1
4 => 4
6 => 6
7 => 7
8 => 8
================================================
I only have you as my tutor. Please guide me. From the description ,
1)How can I rectify this problem?
2)Should I buy a cable?
3)what type of cable should I purchase for the FPGA-Modem?
Please reply to me as soon as possible.

My contact:-
<removed>
Thank you

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Kaustubh Katdare

@thebigk • May 27, 2009

Removing email as we want all the discussions to remain on CE so that larger audience can benefit from them.
0
sauravgoswami

@sauravgoswami-UAfTlI • May 28, 2009

hi Moraali,from your post it seems the cables are fine,please explain in details about your problems??? what is the real issues which is hampering your desire result????
0
moraali

@moraali-tVW4Wl • May 28, 2009

Good morning,

Before I start, I would like to thank you for replying. My problem is simple, but (because I am not from enginnering background) I am not sure how to rectify this problem.
This is my problem:-

1) When I connect my FPGA to the PC , I can perceive they communicate perfecly via hyperterminal.

2) When I connect my Modem to the PC, I can perceive they communicate perfecly via hyperterminal.

3) But when I connect my FPGA to the Modem , I found out they are not communicating.

I can not see what is the problem because they are connected to the PC (hyperterminal is not use).

If you want to more , this below link (I posted to Xilinx forum , but they did not reply me until now) will explain to you the details of my project.

#-Link-Snipped-#

Try to go through it carefully. If you want anything please reply to me as soon as possible.

Thank you.

0
debu

@debu-62iszV • May 29, 2009
@moraali: The problem can lie in two places:
1. The baud rate configuration is incorrect. Many modern modems rely on handshaking signals (RTS & CTS) to determine the auto-baud. There is a possibility that you are not generating these correctly on your FPGA.
2. The Rx and Tx lines are not crossed. Possibly, the cable which you are using for your modem is meant for connecting the modem to your PC. And so is the D9 port on your virtex board.
  
  This is probably the configuration of the cable:
  
  PC Serial Port------------------Modem D9 Port | Modem Internals
  Rx -------------------------------Tx-------------\/---Rx
  Tx -------------------------------Rx-------------/\---Tx
  
  The same cable, if used with the Virtex board will cause the Rx to connect with Rx, and Tx to connect with Tx, as shown below.
  
  Modem D9 Port ----------------Virtex Board D9 Port
  Tx--------------------------------------Tx
  Rx--------------------------------------Rx
  Now, this won't work.
  
  This is the Configuration that you require:
  
  Modem D9 Port ----------------Virtex Board D9 Port
  Tx----------------\/--------------------Tx
  Rx----------------/\--------------------Rx
Hope this helps,

Regards,

Debu 😀
0
moraali

@moraali-tVW4Wl • May 30, 2009

Good evening,

Thank you for replying. I am not from engineering background.

1) May I know what should I do to solve the first question?

2) And for the 2nd question, should the cable(you proposed) be null modem?

Thank you very much.
0
debu

@debu-62iszV • May 30, 2009

@moraali: If the first problem exists, then you will need to implement the handshaking signals in your verilog/vhdl code. Refer to the #-Link-Snipped-# for more information.

Yes, if the second problem exists, a null modem cable should fix it.

Regards,

Debu 😀

0
moraali

@moraali-tVW4Wl • May 30, 2009

Good evening,

Based on above, I like to show the cable connection. I am not sure whether it should be null modem or not. If it should , please let me know.

Basically

1) Modem Port = No Loopback

2) FPGA Port = Loopback (pin 1,4 and 6 are connected together)

So..... should I buy this type of cable?

😕

FPGA ==> Modem
(Female) ==> (Male)

1 ==> 1

2 ==> 3

3 ==> 2

4 ==> 4

5 ==> 5

6 ==> 6

7 ==> 7

8 ==> 8

9 ==> 9

If I am getting it wrong , please correct me. Please reply to me as soon as possible.

Thank you .
0
debu

@debu-62iszV • May 30, 2009

@moraali: Yes, the cable you have shown is a null modem cable, that is what you need.

Regards,

Debu 😀
0
moraali

@moraali-tVW4Wl • May 31, 2009

Good morning,

Thank you very much for your reply. Really appreciate it. I want to send you some pictures. How can I send to you, becasue I can not find any attachment link in this forum?
Please reply to me as soon as possible.

Thank you
0
Kaustubh Katdare

@thebigk • May 31, 2009

Moraali , in order to post the pictures in posts, please first upload them to imageshack and then post the complete URL (ending in file extension) in the alert box that pops up when you click button in the post editor box.

😀
0
moraali

@moraali-tVW4Wl • May 31, 2009

Good morning Mr Debu,
Thank you for your reply. Really appreciate your guide.I am not from engineering , so if my question is annoying , please forgive me. I am just a learner
Based on the Xilinx ML401, I know that the board only support ONE serial port RS232 Db9 (the link is below).

<a href="https://www.monstr.eu/wiki/doku.php?id=boards:ml401:ml401" target="_blank" rel="nofollow noopener noreferrer">Xilinx ML401 [Microblaze Linux/Qemu/U-Boot wiki]</a>

I am planning to create another serial port by using the Expansion Header (if I am wrong please notify me) as shown in the diagram below

1)
I connected the

Power = 5V (not sure, as the above diagram show 3V. Am I correct?)
Ground = Gnd
Tx = J4 (Check the link below)
Rx = J2

#-Link-Snipped-#

2)
Then I did the MAX2323 as shown as the diagram below. Please check, I am not sure whether it is correct or not.

3) Based on the diagram below, I am planning to connect the cable to the PC.

What type of cable should I use as there is no loopback when I try to connect through Expansion Header as show as diagram ?

I am planning to use a male cable port when connecting to MAX2323 for easy shouldering. Would it be a good idea?

PC = Female Port Cable
ExpandionHeader_MAx2323= Male Port Cable

So sorry for to much questions. Please reply to me as soon as possible. The data sheet is in the below link.
#-Link-Snipped-#

Thank you.

0
debu

@debu-62iszV • May 31, 2009

@moraali: Your FPGA doesn't seem to be generating any handshaking signals (atleast according to the schematic, the handshaking signals are looped). Your modem will require these for calcuating the auto-baud. Implement the handshaking signals in your code, and then connect the RI, DCD, RTS and CTS lines, via your MAX232, to the modem.
Hope this helps,

Regards,

Debu 😀
0
Ashraf HZ

@Ash • May 31, 2009

Sorry to be off topic, but.. debu, you have a great blog!
0
moraali

@moraali-tVW4Wl • May 31, 2009

Good evening,

Thank you for your previous reply.

I am not sure what this mean clearly

"
Your FPGA doesn't seem to be generating any handshaking signals (atleast according to the schematic, the handshaking signals are looped). Your modem will require these for calcuating the auto-baud. Implement the handshaking signals in your code, and then connect the RI, DCD, RTS and CTS lines, via your MAX232, to the modem.

"
I am not from engineering background. Could you explain how to do it step by step?

For your info:-

1) For FPGA-Modem via serial port , use this cable

FPGA ==> Modem
(Female) ==> (Male)

1 ==> 1

2 ==> 3

3 ==> 2

4 ==> 4

5 ==> 5

6 ==> 6

7 ==> 7

8 ==> 8

9 ==> 9

2) For FPGA-PC via Expansion Header, use this cable

FPGA ==> PC
(Male) ==> (Female)

1 ==> 1

2 ==> 2

3 ==> 3

4 ==> 4

5 ==> 5

6 ==> 6

7 ==> 7

8 ==> 8

9 ==> 9

Please reply to me as soon as possible.

Thank you.
0
moraali

@moraali-tVW4Wl • May 31, 2009

Good evening,

I am a bit confuse

1)

"Your FPGA doesn't seem to be generating any handshaking signals (atleast according to the schematic, the handshaking signals are looped). "

That means I not need to buy the proposed cable for FPGA-Modem connection?

2)

"
Your modem will require these for calcuating the auto-baud. Implement the handshaking signals in your code, and then connect the RI, DCD, RTS and CTS lines, via your MAX232, to the modem.
"

How can I do this? Should I change the VHDL code?

This is the FPGA RS232 VHDL generated code

-------------------------------------------------------------------------------
-- rs232_uart_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_uartlite_v1_00_a;
use xps_uartlite_v1_00_a.all;
entity rs232_uart_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 1);
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of rs232_uart_wrapper : entity is "xps_uartlite_v1_00_a";
end rs232_uart_wrapper;
architecture STRUCTURE of rs232_uart_wrapper is
component xps_uartlite is
generic (
C_FAMILY : STRING;
C_SPLB_CLK_FREQ_HZ : INTEGER;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end component;
begin
RS232_Uart : xps_uartlite
generic map (
C_FAMILY => "virtex4",
C_SPLB_CLK_FREQ_HZ => 100000000,
C_BASEADDR => X"84000000",
C_HIGHADDR => X"8400ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_SUPPORT_BURSTS => 0,
C_SPLB_NATIVE_DWIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_masterID => PLB_masterID,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrDBus => PLB_wrDBus,
PLB_UABus => PLB_UABus,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_MSize => PLB_MSize,
PLB_lockErr => PLB_lockErr,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_rdDBus => Sl_rdDBus,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MIRQ => Sl_MIRQ,
RX => RX,
TX => TX,
Interrupt => Interrupt
);
end architecture STRUCTURE;

This is the system stub

-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
fpga_0_RS232_Uart_RX_pin : in std_logic;
fpga_0_RS232_Uart_TX_pin : out std_logic;
fpga_0_LEDs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
sys_clk_pin : in std_logic;
sys_rst_pin : in std_logic
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
fpga_0_RS232_Uart_RX_pin : in std_logic;
fpga_0_RS232_Uart_TX_pin : out std_logic;
fpga_0_LEDs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3);
sys_clk_pin : in std_logic;
sys_rst_pin : in std_logic
);
end component;
begin
system_i : system
port map (
fpga_0_RS232_Uart_RX_pin => fpga_0_RS232_Uart_RX_pin,
fpga_0_RS232_Uart_TX_pin => fpga_0_RS232_Uart_TX_pin,
fpga_0_LEDs_4Bit_GPIO_IO_pin => fpga_0_LEDs_4Bit_GPIO_IO_pin,
sys_clk_pin => sys_clk_pin,
sys_rst_pin => sys_rst_pin
);
end architecture STRUCTURE;

Below is the hdl folder

Which part of the VHDL coding should I alter or modify?

Please reply to me as soon as possible.

Thank you
0
debu

@debu-62iszV • Jun 1, 2009

@moraali: You will need to write a module for auto-baud generation (as I stated before). Alternatively, you could use #-Link-Snipped-# for the same. And, yes, you will still need a null modem cable.

Best of luck for your project!

Regards,

Debu 😀

0
moraali

@moraali-tVW4Wl • Jun 1, 2009

Good evening,

Thank you for replying .

When you said

"
Your FPGA doesn't seem to be generating any handshaking signals (atleast according to the schematic, the handshaking signals are looped). Your modem will require these for calcuating the auto-baud. Implement the handshaking signals in your code, and then connect the RI, DCD, RTS and CTS lines, via your MAX232, to the modem.
"
Are you mentioning the commication through Expansion Header only ?

Overall , Do you mean this ?

For FPGA-Modem through Serial Port , I just use null modem cable that you proposed.

And the FPGA-Modem through Expansion Header , I also use the null modem that you proposed and have to change the code.

Please reply to me as soon as possible

Thank you
0
debu

@debu-62iszV • Jun 1, 2009

@moraali: In order to communicate with the modem, you need to use a null modem cable and have you FPGA generate the auto-baud signals.

Regards,

Debu 😀
0
moraali

@moraali-tVW4Wl • Jun 1, 2009

Good morning,

Thank you sir for your reply. I will try.

But do you have any Auto_Baud in vhd? I am not expert in Verilog. Need to learn , and it might take time.

#-Link-Snipped-#

Thank you

0
debu

@debu-62iszV • Jun 1, 2009

@moraali: No, I haven't implemented auto-baud an any FPGA. I posted a link a few posts back of a project which did. You can use that as your reference.

Regards,

Debu 😀
0