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damy7522
damy7522 • Oct 5, 2012

VHDL simulation problem

In model sim, when I compile a program of d-ff, the output does not match when I change the inputs value with respect to clk edge. It shows the correct output when I change the input, with not respect to clk edge means it works as a latch. I attached a file of simulation when i change the input with respect of clk edge. Here reset is active low and these problems do not occur in verilog, using the same software. So please tell me the solution and explain the difference between (clk='1' and clk'event) and (rising_edge(clk)).

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Jeffrey Arulraj
Jeffrey Arulraj • Oct 5, 2012
Rising clock edge refers to Positive edge triggered flip flop
[Prototype]
[Prototype] • Aug 30, 2013
Could you please paste your VHDL code snippet.

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