ZRAM: Say goodbye to DRAM

Presently, the common computer has memory chips made up of DRAM or Dynamic Random Access Memory. The DRAM bit cell stores the memory in form of ‘0’s and ‘1’s in the form of charge on the capacitor. The memory can be read when the transistor that controls access to the capacitor is turned on. By turning on, the transistor allows the charge on capacitor to flow onto a bit line. The voltage thus created is detected and we read the memory.



The fabrication of the DRAM has limitations because the size of capacitor must be big enough to hold a detectable charge. This problem aggravates at about 30nm. The voltage generated by the charge is too small. The design of circuits surrounding the DRAM cell is hence tricky and very sensitive to noise and voltage fluctuations. This could wreck havoc in future when nanotechnology will rule the world.

Innovative Silicon, a Swiss company working with Hynix Semiconductor, has overcome this hurdle and developed the ZRAM or Zero Capacitor RAM. The interesting thing of ZRAM is that instead of using a transistor to control the charge storing capacitor, a single transistor employing “floating body” effect is used. The technology is called silicon-on-insulator or simply SOI technology.

[*]The floating body refers to the floating charge. Firstly, a transistor is built in a layer of silicon.
[*] Now this is deposited on the top of silicon dioxide which is an insulator.
[*]Electrons create electron hole pairs when current passes through the transistor.
[*]The extra holes are left by the transistors drain but the holes are trapped.
[*]These trapped holes create a resultant net positive charge. This charge is floating and can be read as ‘1’.
[*]We can read ‘0’ by increasing the voltage at transistor gate which empties the holes through the source electrode.
[*]This technique to read the memory does not require capacitors and the bit cell need to be as small as the transistors. The size of transistor is reducing day by day. So size of transistor is not a problem.

Using SOI wafer technology to build the device escalated the cost. So the company, instead of mounting the transistor on top of on insulating layer, with the gate on top and the source and drain on ends, uses newer alignment technique. Now, the transistor is aligned vertically so that the gates are on either side and the junctions are at the top and bottom. This resulted in following advantages:

[*]Same isolation and floating body effect is achieved.
[*]Moving towards enrichment of 3D transistor oriented industry.
[*]The vertical design with the novel placement of gate results in operating voltage of 0.5 volts. This operating voltage is claimed to be 50 to 75 percent lower than any other floating body memory device.
[*]The design is a very energy efficient and is therefore compatible with existing power supplies.
[*]The amount of time a cell can hold onto a bit amid noise of other cells switching is improved by a factor of 1000.
[*]As the Z-RAM cell is made up of only one transistor as compared to SRAM’s six, it can hold five times as many bits on the same area of silicon.

Hynix Semiconductor has got the license for the commercial production of ZRAM and is expected to roll out the same within two years.