james david
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Jan 6, 2008
Last active
Feb 23, 2008
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Recent posts
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@james-david-Sigiph • Oct 26, 2024Oct 26, 20242.4K
Edge Detection using VHDL/Verilog
Hello VLSI Design Engineers, We are a group of students doing M.S in VLSI Design. For one of our mini projects, we tried implementing...