Where is HDL subsystem in DSP builder

Hi,

I am new to DSP builder and FPGA programming. I was following DSP builder example which was on implementing FIR filter using DSP builder in Simulink and generating VHDL to be implement in my cyclone 2 FPGA. I came across this block as was given in the example steps which was "HDL SubSystem block" but I can't seem to find this block in my DSP builder library... could someone tell me what is wrong... I even tried reinstalling DSP builder..

here is the tutorial that I have been using to design me FIR filter using simulink.... its on page 39 step 10 from adobe file....its on the 2nd section Implementing DSP design using FPGA....
here is the link #-Link-Snipped-#