Instruction cache memory VS data cache memory

@rukawa-Y0pUkC • Oct 25, 2024

Oct 25, 2024

1.6K

Hello everyone,
which is bigger normally : the instruction cache memory or the data cache memory? (Say for level 1 cache for example)

Like 0 Replies 8

Replies

Welcome, guest

Join CrazyEngineers to reply, ask questions, and participate in conversations.

CrazyEngineers powered by Jatra Community Platform

rukawa

@rukawa-Y0pUkC • Jan 5, 2014

Can somebody please answer me?
0
[Prototype]

@prototype-G9Gn5k • Jan 5, 2014

L1 cache for both Data and Instructions are of same size.
0
J Biswas

@j-biswas-SBo0im • Jan 5, 2014

CISC or RISC ??? Which you you need the answer for?
0
rukawa

@rukawa-Y0pUkC • Jan 6, 2014

J Biswas
CISC or RISC ??? Which you you need the answer for?
RISC and CISC if possible
0
rukawa

@rukawa-Y0pUkC • Jan 6, 2014

[Prototype]
L1 cache for both Data and Instructions are of same size.
Thanks for your answer
0
J Biswas

@j-biswas-SBo0im • Jan 6, 2014

In RISC DC blocks are nearly 8 to 16 times (or even) more than IC blocks. This helps in single cycle instructions. The Level1 register set, for DC is almost similar or sometimes more than IC blocks in CISC processors. Architecture in CISC chosen, governs.

- JB -
0
rukawa

@rukawa-Y0pUkC • Jan 7, 2014

J Biswas
In RISC DC blocks are nearly 8 to 16 times (or even) more than IC blocks. This helps in single cycle instructions. The Level1 register set, for DC is almost similar or sometimes more than IC blocks in CISC processors. Architecture in CISC chosen, governs.

- JB -
Thank you. Do you know some articles or books which talk about cache performance?
0
J Biswas

@j-biswas-SBo0im • Jan 7, 2014

Not quite sure of market available text / design books dear, I never read any myself........we did L2 and L3 cache designs at Intel and AMD long time back. My knowledge is restricted only to a few processor families. I learnt from those company's architecture books.
L1 register designs are controlled solely on the processor feature listing (speed, calc. capacity, opcode movements, machine cycle restrictions etc.) and usage. Different processors have different architectures.
0