CrazyEngineers
CrazyEngineers
Howdy guest!
Dear guest, you must be logged-in to participate on CrazyEngineers. We would love to have you as a member of our community. Consider creating an account or login.
Replies

  • rukawa

    Member • Jan 5, 2014

    Can somebody please answer me?
    Are you sure? This action cannot be undone.
    Cancel

  • [Prototype]

    Member • Jan 5, 2014

    L1 cache for both Data and Instructions are of same size.
    Are you sure? This action cannot be undone.
    Cancel

  • J Biswas

    Member • Jan 5, 2014

    CISC or RISC ??? Which you you need the answer for?
    Are you sure? This action cannot be undone.
    Cancel

  • rukawa

    Member • Jan 6, 2014

    J Biswas
    CISC or RISC ??? Which you you need the answer for?
    RISC and CISC if possible
    Are you sure? This action cannot be undone.
    Cancel

  • rukawa

    Member • Jan 6, 2014

    [Prototype]
    L1 cache for both Data and Instructions are of same size.
    Thanks for your answer
    Are you sure? This action cannot be undone.
    Cancel

  • J Biswas

    Member • Jan 6, 2014

    In RISC DC blocks are nearly 8 to 16 times (or even) more than IC blocks. This helps in single cycle instructions. The Level1 register set, for DC is almost similar or sometimes more than IC blocks in CISC processors. Architecture in CISC chosen, governs.

    - JB -
    Are you sure? This action cannot be undone.
    Cancel

  • rukawa

    Member • Jan 7, 2014

    J Biswas
    In RISC DC blocks are nearly 8 to 16 times (or even) more than IC blocks. This helps in single cycle instructions. The Level1 register set, for DC is almost similar or sometimes more than IC blocks in CISC processors. Architecture in CISC chosen, governs.

    - JB -
    Thank you. Do you know some articles or books which talk about cache performance?
    Are you sure? This action cannot be undone.
    Cancel

  • J Biswas

    Member • Jan 7, 2014

    Not quite sure of market available text / design books dear, I never read any myself........we did L2 and L3 cache designs at Intel and AMD long time back. My knowledge is restricted only to a few processor families. I learnt from those company's architecture books.
    L1 register designs are controlled solely on the processor feature listing (speed, calc. capacity, opcode movements, machine cycle restrictions etc.) and usage. Different processors have different architectures.
    Are you sure? This action cannot be undone.
    Cancel
Home Channels Search Login Register