Digital System Design Problem

Can anyone help me out with this question:-

Design a circuit that takes a serial data stream from data in input.The output of the circuit is high if data in on previous four clocks has even number of ones??


  • cranky
    I am not too sure about this.But here is my take:
    Consider the first input is A,followed by B,C and D.When (A ^ B ^ C^ D)'output is sent through "NOT" gate,the output would be the same as the question. It also states that the output is turned at every fourth clock cycle.So,we could use four registers( or a counter ) to send this signal.
    Someone please clarify 😀
  • Adivy
    Could you please explain in detail about considering ABCD as inputs?I dont get it?
    Following is what I understood from the question:-
    firstly since it is talking about serial data in so i think we need to use registers as you said.Secondly as it deals with previous clocks we need to design a sequential circuit.
    As a whole, the output on nth clock is high if the data-in on clocks (n-1),(n-2),(n-3)&(n-4) has even number of ones.
  • Adivy
    Someone please help??
  • MjWasHere
    @Adivy : Did you get any answer to this question yet ? Mind sharing ?
  • Adivy
    I didnt get any answer.
    CEans please help us out with this problem.

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