naz123
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- Member since
- Oct 15, 2014
- Last active
- Dec 3, 2014
- Total activities
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#Threads
e767c003-4f30-4172-89e8-d5e1ff9be701
Jeffrey SamuelIn Test bench mate Main module you will have only input and output ports Test bench has inout ports as well...
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#Threads
c57ad4aa-e8c8-4ccc-84ec-38050800510c
Thanks for your reply Jeffrey. I tried.. but m not able to load text file values as an input to the inout...
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#Threads
2d5e3155-6e6d-4361-8e4f-46efec96887b
hi can anyone please tell how to assign the pixel values stored in text file to an inout port in verilog code?...
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#Threads
7c52bd09-c9ec-45be-9eb4-23a272207110
can any one please tell me how to write verilog code for gaussian filter. Thanks in advance.
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#Threads
9057808e-7f24-4e36-9bfb-704e818bd06c
sir .i want to implement edge detection using canny algorithm in verilog . i am very much interested to do this project...