Xilinx CPLD, decoupling capacitors
@andrew1-VrpXAJ
•
Oct 22, 2024
Oct 22, 2024
1.7K
Hi Everyone,
I am working on a small PCB with a Xilinx CPLD xc95288xl on it;
it will be a part of a switchboard matrix for an FPGA based multiprocessor which
I am working on as a hobbyist.
I would like to have your help on this problem:
should each Vccint and also Vccio pin have decoupling capacitors ?
Xilinx in his 'xapp112' application note says: decouple all device Vcc pins (maybe it refers only to Vccint pins ...)
Does any one have direct experience ? Thank you.
I am working on a small PCB with a Xilinx CPLD xc95288xl on it;
it will be a part of a switchboard matrix for an FPGA based multiprocessor which
I am working on as a hobbyist.
I would like to have your help on this problem:
should each Vccint and also Vccio pin have decoupling capacitors ?
Xilinx in his 'xapp112' application note says: decouple all device Vcc pins (maybe it refers only to Vccint pins ...)
Does any one have direct experience ? Thank you.