VLSI Problem - Need Solution

Design a CMOS inverter chain as a clock buffer which drives the first stage of clock tree with equivalent interconnect parasitic capacitance of 1nF. The input gate capacitance of the inverter is 50fF. Device model parameter and unit equivalent resistance (average equivalent resistance may be used) can be found in the unified model. The unit capacitance is 15fF and gamma(r) = 1.

(1) Find the number of stages required when the effective fan-out are e, 4 and 6,respectively. Calculate the corresponding inverter chain delay.

(2) Which case in (1) gives the lowest path delay? Estimate the W of the last inverter in the chain (L=0.25mm). Assume that the first inverter has device sizesof W/L=2 for PMOS and W/L=1 for NMOS.

(3) Estimate the total dynamic power dissipation if the clock frequency is 1GHz and VDD = 2.5V

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P.S. I need the solution for part (b).. Getting absurd result.. Tried everywhere on my own... Finally to CE 😀

Cheers,
Prakash