Synthesis and Simulation

sarveshgupta

sarveshgupta

@sarveshgupta-txtmu5 • Oct 24, 2024
What is the difference between synthesis and simulation?

I am asking in context to VHDL hardware modeling programming

Is there anything behavioral or functional simulation also? 😕
Like 0 Replies 1

Replies

Welcome, guest

Join CrazyEngineers to reply, ask questions, and participate in conversations.

Sign up Log in

CrazyEngineers powered by Jatra Community Platform

  • patsham

    patsham

    @patsham-AsXMka • Dec 14, 2009

    hey synthesis means execution of the vhdl code...and simulation means where the software tests your circuit design,preparing a code for it...

    [​IMG]