Synthesis and Simulation
What is the difference between synthesis and simulation?
I am asking in context to VHDL hardware modeling programming
Is there anything behavioral or functional simulation also? 😕
I am asking in context to VHDL hardware modeling programming
Is there anything behavioral or functional simulation also? 😕
Replies
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patshamhey synthesis means execution of the vhdl code...and simulation means where the software tests your circuit design,preparing a code for it...
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