hello,

In an n channel JFET why is it that a reverse bias existing between the gate and the source despite the fact that we are shorting the gate and source terminals and keeping Vds as a positive quantity. Now a general explanation would be due to presence of a voltage divider that manifests the properties of the n type conducting channel, but then in that case the bias(between the gate and the source) should have been a positive one. We are applying a positive polarity at the drain(of Vds) and a negative polarity(of Vds) at the source. of course this polarity has nothing to do with the after effects of this biasing method but why this anomaly?

thanks