Reverse bias in N Channel JFET

pratap singh,
Member • Oct 7, 2013

Reverse bias in N Channel JFET

hello,

In an n channel JFET why is it that a reverse bias existing between the gate and the source despite the fact that we are shorting the gate and source terminals and keeping Vds as a positive quantity. Now a general explanation would be due to presence of a voltage divider that manifests the properties of the n type conducting channel, but then in that case the bias(between the gate and the source) should have been a positive one. We are applying a positive polarity at the drain(of Vds) and a negative polarity(of Vds) at the source. of course this polarity has nothing to do with the after effects of this biasing method but why this anomaly?

thanks

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Jeffrey Arulraj

Member • Oct 10, 2013

proffy
hello,

In an n channel JFET why is it that a reverse bias existing between the gate and the source despite the fact that we are shorting the gate and source terminals and keeping Vds as a positive quantity.
Know this
Vgs=Vg- Vs
Where Vg = Voltage at the gate
Vs = Voltage drop at the source resistor
When we short the Gate terminal and source we have Vg=0

This implies Vgs= -Vs

That explains the negative voltage at gate terminal

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Jeffrey Arulraj

Member • Oct 10, 2013

You must know that Vs= IdRs
Id= Drain current which is the same as that off Source current
Rs= Resistance at the source terminal

You must know that the drain current is purely because of the Positive voltage at the Vds

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