Researchers' Paper On Computer Architecture Wins Best Paper Award 2011
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Oct 16, 2024
Oct 16, 2024
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A paper written by Dr. Paul Gratz, an assistant professor and his graduate student, Reena Panda, hailing from the Department of Electrical and Computer Engineering at Texas A&M University have won the prestigious IEEE Paper Of The Year award for their work on <em>"B-Fetch: Improving Future Computer System Energy-Efficiency and Performance and through Efficient and Accurate Memory System Speculation."</em> All papers that feature in <em>IEEE</em> Computer Architecture<em> Letters</em> in 2011 were eligible for the award, but only a few were shortlisted by a committee of the journal and HPCA representatives.
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Their paper focuses primarily on energy efficiency which is one of the most important aspects in any field. Computer Science has been steadily working to pass this barrier. Manufacturers have switched to chip-multiprocessor designs, many processor cores and the concept of fusion chips only to keep power consumption minimal. But the low power consumption has come with a price to pay in the form of performance of individual threads. When compiling high level languages, like C++ and Java, they are converted to assembly language.  In assembly, data transfer between the main memory and the processor is explicit and this often becomes a performance constraint.
Chip multiprocessors, though use Data Pre-fetching in order to avoid any power-hungry speculative techniques, many such schemes either need a high overhead in power and area or perform unsatisfactorily with some applications. In light of such issues, the paper proposes  a new data-prefetching scheme known as B-Fetch. Designed for lightweight, in-order processors, B-Fetch effectively addresses value speculation. Apparently, with this approach a better performance is extracted with only one-third the power and area of the best data-prefetching schemes available right now.
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Their paper focuses primarily on energy efficiency which is one of the most important aspects in any field. Computer Science has been steadily working to pass this barrier. Manufacturers have switched to chip-multiprocessor designs, many processor cores and the concept of fusion chips only to keep power consumption minimal. But the low power consumption has come with a price to pay in the form of performance of individual threads. When compiling high level languages, like C++ and Java, they are converted to assembly language.  In assembly, data transfer between the main memory and the processor is explicit and this often becomes a performance constraint.
Chip multiprocessors, though use Data Pre-fetching in order to avoid any power-hungry speculative techniques, many such schemes either need a high overhead in power and area or perform unsatisfactorily with some applications. In light of such issues, the paper proposes  a new data-prefetching scheme known as B-Fetch. Designed for lightweight, in-order processors, B-Fetch effectively addresses value speculation. Apparently, with this approach a better performance is extracted with only one-third the power and area of the best data-prefetching schemes available right now.
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