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A Low-Power Small-Area 1-bit Full Adder Cell in a 0.35μm CMOS Technology for Biomedical Oriented System-on-Chip Applications. Because addition operations are extensively used in digital signal processing, a low-power small-area 14-transistor 1-bit adder cell with rail-to-rail output swing is presented. The cell is designed and laid out in a 0.35μm 3.30V CMOS technology and is meant to replace the 28-transistor 1-bit standard CMOS adder [3] provided by the technology supplier. Several few-transistor-count adder cells have been proposed in the literature [4]-[5], but have the disadvantage of demanding more than 14 transistors, which negatively impact the area of the cell, or of not producing full swing output signals, which worsens the noise margin and the driving capability of the cell, and makes subsequent buffering stages dissipate considerable amounts of power.
Recently, there exist opportunities in semiconductor devices, materials, and related control technologies that will enable production of low-cost power electronics with dramatically reduced size. To make full use of these developments, the concept of an intelligent power module has evolved, the Power Electronic Building Block (PEBB), which is envisioned as a standard programmable device to carry out a variety of power electronic applications such as motor drives, ship service inverters, and integral starter generators for aircrafts.
A Voltage to current transducer in CMOS Technology and some Applications". The work involved studying a Voltage to Current Transducer(VCT), analysis of VCT in terms of the dynamic range, frequency response, designing a driver network to improve the dynamic range of VCT, using VCT to realize a voltage mode and a current mode low-pass filter.