power analysis after digital synthesis(vlsi) using cadence s/w
😉 I have been doing a low power vlsi design of comparator(4 bit) for precomputation for my 8th sem project . I want to analyse the power at digital synthesis stage ,also show that precomputation for comparator has reduced power but not able to know how to proceed with it for the front end design.Moreover ,we have not started with our back end design for precomputation using soc design. Can anyone suggest how to proceed with our project and what else can we include?
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