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New Prefetching Criteria Make Multi-Core Chips Faster And Bandwidth Efficient
Scientists and computer analysts at the North Carolina State University have successfully implemented two novel bandwidth management schemes that help to enhance the efficiency of multi core processor chips. These two new technologies facilitate faster data retrieval by the individual cores and allow superfast operation of the entire system. The main differences between this new technique and the conventional methods are the bandwidth allocation and pre-fetching data. It is expected that these changes will step up the chip efficiency by at least 40%. The research work will be presented as the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS) in San Jose, California on 9th June in the form of a paper titled "Studying the Impact of Hardware Prefetching and Bandwidth Partitioning in Chip-Multiprocessors".
![[IMG]](proxy.php?image=http%3A%2F%2Fwww.crazyengineers.com%2Fwp-content%2Fuploads%2F2011%2F05%2Fprefetching.jpg&hash=ee9c1b9c1ec72f5ec7a8093c6b2bacc6)
The main idea behind the design of multi core computer chips is that they allow the machines to operate at amazingly great speeds. To make it possible, the design incorporates a specific CPU for each core i.e. each core has its own brain. But sometimes, the core is required to fetch some information that’s not available in its memory. Such data has to be retrieved from somewhere else and it tends to slow down the chip. For data retrieval, each core has a predetermined channel bandwidth which it can use for information transfer. As the number of cores in a chip is increasing, the bandwidth spectrum has become congested and difficult to manage.
The North Carolina research team has identified prefetching as a feasible solution to this problem. Each chip has a cache memory. In prefetching, the cache governs an algorithm which is capable of predicting the data that will be required by the core in future. The algorithm also fetches the data beforehand. If we consider the perfect case, the method is bound to increase the efficiency dramatically. However, if these predictions go wrong, the same process will slow down the chip. So it is like a double edged sword.
The first technique allocates variable bandwidths to different cores because the off chip data to be fetched by all cores is not uniform. Dr. Yan Sohilin, an associate professor of electrical and computer engineering at NC State and co-author this research paper believes that hardware counters could be used to find out which cores require more bandwidth. This leads to an optimal performance by all the chip subsystems without any wastage of the available channels.
The second technique is basically a set of conditions that would determine whether the prefetching is boosting the efficiency or reducing the speed of the processor. These prefetching criteria will be present in every multi core processor chip. The core will automatically turn the prefetching logic on or off depending on its effect on the actual performance of the chip. This scheme will be 40% more efficient than chips that never prefetch and 10% better than chips that always perform prefetching.
Image credit: ixtb labs
![[IMG]](https://www.crazyengineers.com/wp-content/uploads/2011/05/prefetching.jpg)
The main idea behind the design of multi core computer chips is that they allow the machines to operate at amazingly great speeds. To make it possible, the design incorporates a specific CPU for each core i.e. each core has its own brain. But sometimes, the core is required to fetch some information that’s not available in its memory. Such data has to be retrieved from somewhere else and it tends to slow down the chip. For data retrieval, each core has a predetermined channel bandwidth which it can use for information transfer. As the number of cores in a chip is increasing, the bandwidth spectrum has become congested and difficult to manage.The North Carolina research team has identified prefetching as a feasible solution to this problem. Each chip has a cache memory. In prefetching, the cache governs an algorithm which is capable of predicting the data that will be required by the core in future. The algorithm also fetches the data beforehand. If we consider the perfect case, the method is bound to increase the efficiency dramatically. However, if these predictions go wrong, the same process will slow down the chip. So it is like a double edged sword.
The first technique allocates variable bandwidths to different cores because the off chip data to be fetched by all cores is not uniform. Dr. Yan Sohilin, an associate professor of electrical and computer engineering at NC State and co-author this research paper believes that hardware counters could be used to find out which cores require more bandwidth. This leads to an optimal performance by all the chip subsystems without any wastage of the available channels.
The second technique is basically a set of conditions that would determine whether the prefetching is boosting the efficiency or reducing the speed of the processor. These prefetching criteria will be present in every multi core processor chip. The core will automatically turn the prefetching logic on or off depending on its effect on the actual performance of the chip. This scheme will be 40% more efficient than chips that never prefetch and 10% better than chips that always perform prefetching.
Image credit: ixtb labs