# Need Explanation of this Master Slave D Flip Flop

Please look @ the pictures below. I have drawn a master slave D flipflop with preset and clear option as mentioned in the book.

Can any one tell me what is the necessity of the wires that are highlighted in the image? isn't the wire @ last stages of NAND gates enough?

## Replies

• KenJackson
u_know_who
... as mentioned in the book.
The book? Which book?

It's been quite a while since I've even looked at a logic diagram like this. Am I correct in assuming that both inputs labeled 1 are tied together? And that both inputs 0 and 1 are normally false and that 1 is pulsed true to preset one output state and 0 is pulsed true to preset the other ("clear")?

There are two memory elements in the diagram.
U5 and U6 form one memory element, while U7 and U8 form another.
If you are going to set a state, I expect you would have to affect both elements.

Also, the signal takes some finite amount of time to pass through any gate. Sometimes you need redundant terms to avoid a glitch (very brief change of state) on the output.
• u_know_who
Book name : "Fundamentals of Digital Logic with Verilog Design"
Writer name : Stephen Brown & Zvonko Vranesic.

This master slave is comprised of two gated D latch (so only one input : D). in the slave inactive stage (clock = 1) it is easy to make Q = 0 (output of U7) by pressing clear = 0 (the third logicstate). But it becomes tough to explain how to make Q = 0 when slave stage is active (clock = 0).
• u_know_who
Book name : "Fundamentals of Digital Logic with Verilog Design"
Writer name : Stephen Brown & Zvonko Vranesic.

This master slave is comprised of two gated D latch (so only one input : D : the middle logicstate). in the slave inactive stage (clock = 1) it is easy to make Q = 0 (output of U7) by pressing clear = 0 (the third logicstate). But it becomes tough to explain how to make Q = 0 when slave stage is active (clock = 0).

You are reading an archived discussion.

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