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help me out with this VHDL program

[​IMG] trying to understand VHDL programs ..please help
i am a 3rd year student of ece dept...i m doing a project on this topic.....i am seeking someone's help to understand the VHDL program stepwise,which is listed below....
-- Design Name:
-- Module Name: ALU_Controller controls alu components bases off inputs
-- Project Name: DSD_Project (4 bit alu)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU_Controller is
Port( opcode : in std_logic_vector(1 downto 0); -- opcode and mode in
mode : in std_logic; -- mode
output : out std_logic_vector(5 downto 0)); -- all the outputs
end ALU_Controller;

architecture Behavioral of ALU_Controller is
type arrayRom is array (0 to 7) of std_logic_vector (5 downto 0);
constant Rom: arrayRom := ("000100","001010","000010","000000",
"000001","010001","100001","110001");

begin

output <= Rom(conv_integer(mode & opcode));
end Behavioral;

please help!!😕

Replies

  • PhilippeFaes
    PhilippeFaes
    It is a ROM module, evidently used as decoder in an ALU (Arithmetic Logic Unit) in a processor. The input is the opcode (2 bits) and the mode (1 bit). These bits are concatenated (& operator) to for a 3 bit address into the ROM.

    Using 3 bits, you can address 8 data words. For example, if the mode is '1' and the opcode is '01', this module will return the data in ROM address b"101" (or: 5). The output will be: "010001". Note that the adresses start counting at 0, so address position 5 is actually the 6th data element.

    kind regards

    --
    Philippe
    Upfront Verification - Sigasi, the future of VHDL

    [​IMG]

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