FPGA IMPLEMENTATION OF LOW POWER AND HIGH SPEED FFT ARCHITETURE
@gomathi-palanisamy-hMeBtk
•
Oct 26, 2024
Oct 26, 2024
1.5K
Project Abstract / Summary : Discrete Fourier Transform (DFT) is one of the most employed blocks in many communication and signal processing systems. FFT (Fast Fourier Transform) is a highly efficient procedure to reduce computation time and also improves the performance in DFT. The Radix 22, 23 and 24 FFT architectures are not efficient because of its low utilization of components. In Our aim to design a high data throughput and low complexity VLSI structure for Radix 25 FFT architecture. The decimation in time equations are reviewed and sequence of several FPGA modules are presented according to algorithm architecture. Most of previous architectures were designed using the complex booth multipliers, but our proposed architecture uses canonical signed digit (CSD) multiplier circuit which is used to improve performance and also increase the accuracy of the output. In this complete architecture simulated in Xilinx ISE system edition software and implemented in Xilinx SPARTAN-6 FPGA kit. To optimize the power, area and speed of the signal process, pipelining and parallel processing techniques have to be used in this proposal.
Why did you choose to work on this project topic : Today the technology based on hardware and power efficiency for high performance. Application such as digital signal processing, communications etc.
OFDM(orthogonal frequency division multiplexing) is one of most important concept in digital communication system. In which DFT is one of the block.To increase the speed of DFT which leads to increase the speed of communication system. Fast Fourier Transform(FFT) is best technique to implement this concept which help to improve the speed of process..
Power is another major constrain to increase the performance. In our proposal canonical signed digit multiplier is used to reduce the power.
So, in this project, we are implement the high speed and low power Radix 2^5 FFT architecture.
Project Category : Electrical / Electronics / Communication
------------------------------------------------------
Institute/College Name: KNOWLEDGE INSTITUTE OF TECHNOLOGY
City: SALEM
State: TAMILNADU
Participating Team From: Final Year
Why did you choose to work on this project topic : Today the technology based on hardware and power efficiency for high performance. Application such as digital signal processing, communications etc.
OFDM(orthogonal frequency division multiplexing) is one of most important concept in digital communication system. In which DFT is one of the block.To increase the speed of DFT which leads to increase the speed of communication system. Fast Fourier Transform(FFT) is best technique to implement this concept which help to improve the speed of process..
Power is another major constrain to increase the performance. In our proposal canonical signed digit multiplier is used to reduce the power.
So, in this project, we are implement the high speed and low power Radix 2^5 FFT architecture.
Project Category : Electrical / Electronics / Communication
------------------------------------------------------
Institute/College Name: KNOWLEDGE INSTITUTE OF TECHNOLOGY
City: SALEM
State: TAMILNADU
Participating Team From: Final Year