Radhika
Member • Jul 12, 2011
Anna University - Question Paper for VI sem -ADVANCED COMPUTER ARCHITECTURE
B.E/B.TECH DEGREE EXAMINATION,APRIL/MAY 2011
SIXTH SEMESTER
Computer science and engineering
CS 2354- ADVANCED COMPUTER ARCHITECTURE
(Regulation 2008)
Time: three hours maximum:100 marks
Answer ALL questions
PART A(2*10=20 marks)
1. what is loop unrolling? and what are its advantages?
2. differentiate between static and dynamic branch predication approaches.
3. what is fine-grained multithreading and what is the advantage and disadvantages of fine -grained multithreading?
4. what a VLIW processor?
5. what is sequential consistency?
6. state the advantages of threading.
7. differentiate between write-through cache and snoopy cache.
8. compare SDRAM with DRAM.
9. what is multi-core processor and what are the application areas of multi-core processors?
10.what is Cell Processor?
PART B(5*16=80 marks)
11. (a) Briefly describe any techniques to reduce the cokntrol hazard stalls.(16)
or
(b) (i) discuss about any two compiler techniques for exposing ILP in detail(8)
(ii) Explain how ILP is achieved using dynamic scheduling(8)
12. (a) (i) describe the architectural features of IA64 Processors in detail(10)
(ii) Explain the architecture of a typical VLIW processor in detail(6)
or
(b)(i) describe the architectural features of Itanium Processor(10)
(ii) Explain how instruction level parallelism is achieved in Epic processor(6)
13. (a) (i) describe the basic structure of a centralized shared-memory multiprocessor in detail(6)
(ii) describe the implementation of directory-based cache coherence protocol(10)
or
(b) (i) what are the advantages and disadvantages of distributed-memory multiprocessors? describe the basic structure of a distributed memory multiprocessor in detail.(8)
(ii) describe sequential and relaxed consistency model(6)
14. (a)(i) with suitable diagram, explain how virtual address is mapped to L2 cache address.(10)
(ii) Discuss about the steps to be followed in designing I/O system(6)
or
(b) describe the optimization techniques used in compiler to reduce cache miss rate(16)
15. (a)(i) Describe the feature of SUN CMP architecture in details(6)
(ii) what are multi core processors? explain how a multi core processors works. (10)
or
(b) (i) discuss aboyt the SMT kernel Structure in detail(8)
(ii) describe the architecture of the IBM cell Processor in detail(8)
SIXTH SEMESTER
Computer science and engineering
CS 2354- ADVANCED COMPUTER ARCHITECTURE
(Regulation 2008)
Time: three hours maximum:100 marks
Answer ALL questions
PART A(2*10=20 marks)
1. what is loop unrolling? and what are its advantages?
2. differentiate between static and dynamic branch predication approaches.
3. what is fine-grained multithreading and what is the advantage and disadvantages of fine -grained multithreading?
4. what a VLIW processor?
5. what is sequential consistency?
6. state the advantages of threading.
7. differentiate between write-through cache and snoopy cache.
8. compare SDRAM with DRAM.
9. what is multi-core processor and what are the application areas of multi-core processors?
10.what is Cell Processor?
PART B(5*16=80 marks)
11. (a) Briefly describe any techniques to reduce the cokntrol hazard stalls.(16)
or
(b) (i) discuss about any two compiler techniques for exposing ILP in detail(8)
(ii) Explain how ILP is achieved using dynamic scheduling(8)
12. (a) (i) describe the architectural features of IA64 Processors in detail(10)
(ii) Explain the architecture of a typical VLIW processor in detail(6)
or
(b)(i) describe the architectural features of Itanium Processor(10)
(ii) Explain how instruction level parallelism is achieved in Epic processor(6)
13. (a) (i) describe the basic structure of a centralized shared-memory multiprocessor in detail(6)
(ii) describe the implementation of directory-based cache coherence protocol(10)
or
(b) (i) what are the advantages and disadvantages of distributed-memory multiprocessors? describe the basic structure of a distributed memory multiprocessor in detail.(8)
(ii) describe sequential and relaxed consistency model(6)
14. (a)(i) with suitable diagram, explain how virtual address is mapped to L2 cache address.(10)
(ii) Discuss about the steps to be followed in designing I/O system(6)
or
(b) describe the optimization techniques used in compiler to reduce cache miss rate(16)
15. (a)(i) Describe the feature of SUN CMP architecture in details(6)
(ii) what are multi core processors? explain how a multi core processors works. (10)
or
(b) (i) discuss aboyt the SMT kernel Structure in detail(8)
(ii) describe the architecture of the IBM cell Processor in detail(8)