flukei

flukei

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Member since
Jun 28, 2009
Last active
Jul 1, 2009
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  1. #Threads

    10f2bff7-2639-480a-8d6d-7cca0baf56dd

    It worked on Altera's Quartus II and I was using verilog I guess my code couldnt be used for VHDL coding thank...

  2. #Threads

    258939d1-6668-494d-8a42-e6e18828d621

    It is a state machine that replaces always@(posedge..) and always@(negedge..) verilog command, It checks if your values are going from high to...

  3. #Threads

    b21af63c-33f1-4c06-bba9-9a73760765e3

    please note: in1 is the net/signal you want to detect its transition the line with state<=in_state can be replaced with your code...

  4. #Threads

    b950a24e-e405-4e80-a859-69d20275ebde

    I am using Quartus II and you cant have more than always@(posedge/negedge) so i came up with a state machine edge detector...