It worked on Altera's Quartus II and I was using verilog I guess my code couldnt be used for VHDL coding thank you for your feedback

It is a state machine that replaces always@(posedge..) and always@(negedge..) verilog command, It checks if your values are going from high to low or low to high I used it...

please note: in1 is the net/signal you want to detect its transition the line with state<=in_state can be replaced with your code that should be executed at negedge if you...

I am using Quartus II and you cant have more than always@(posedge/negedge) so i came up with a state machine edge detector it executes your code when at state s1...