Stanford Scientists Create Futuristic Flash Memory Cell
"<em>640 k ought to be enough for anyone</em>" were the famous words of Bill Gates himself. Now call it determination of Mr. Gates or say that "time is powerful" that even the most common PCs have their memory in GB and we still are hungry for more. The Computing world is ever changing and the area of storage and memory has also seen many important developments. This time scientists have succeeded in achieving a great feat. Though not in increasing memory capacity but in upgrading its quality by miniaturizing the silicon cells. In an important innovation Scientists from Stanford University have recently found an alternative to the flash memory-the one currently used everywhere from Smartphones to Tablets. The researchers were able to design two technologies- <em>The Resistive Random access memory</em> (RRAM) and <em>The</em> <em>Phase change memory </em><em>(PCM). </em>The research was led by IEEE fellow Prof. H.S Philip Wong.
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High temperature region simulation above carbon electrode as used in Phase change memory
The scientists from Stanford University wanted to create a non volatile memory which eventually saves power in reading and writing small sets of bits unlike flash which consumes more power. Â The line of action for miniaturizing the memory cell was based upon the concept of implanting nanotubes on Silicon. This was done by first growing nanotubes on quartz. Then applying a layer of Gold and later on etching away the Gold after packing it with a layer of Silicon; the Gold layer, not being thicker than 100 nanometers. By using this method, the team could design a 6X6 nanometer RRAM cell which composed of a layer of Aluminum oxide between two crosshatched layers of nanotubes. The working of this cell depends on the quantity of voltage created across it. The memory cell so constructed is sensitive to 10V and 10Â ma current.
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A schematic illustration of resistive random access memory
For developing the Phase change memory, Wong and his colleagues chose materials like Tellurium, Germanium and Antimony. The memory cell in this case was found to be even more sensitive. A cell of 2.5 nm² area responded to a current of 1.4 µA changing its nature to amorphous state from its normal crystalline form. The amorphous form also having more resistance than its crystalline form.
Until now, designing silicon memory cells with sizes less than 16 nm was not feasible owing to the fact that there was always a chance of charge leakage or damaging nano memory cell. The team has come to conclusion of sandwiching the PCM material between bottom and top electrodes, making it more compact than the previous versions. The miniaturization would thus result in efficient and less power consuming memory cell. However, its durability is yet to be tested. Further research would make it more reliable after which we can see it replacing today's flash memory. The current work of scientists in this regard was presented in <em>2011 Symposium on VLSI technology, Kyoto</em>.
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High temperature region simulation above carbon electrode as used in Phase change memory
The scientists from Stanford University wanted to create a non volatile memory which eventually saves power in reading and writing small sets of bits unlike flash which consumes more power. Â The line of action for miniaturizing the memory cell was based upon the concept of implanting nanotubes on Silicon. This was done by first growing nanotubes on quartz. Then applying a layer of Gold and later on etching away the Gold after packing it with a layer of Silicon; the Gold layer, not being thicker than 100 nanometers. By using this method, the team could design a 6X6 nanometer RRAM cell which composed of a layer of Aluminum oxide between two crosshatched layers of nanotubes. The working of this cell depends on the quantity of voltage created across it. The memory cell so constructed is sensitive to 10V and 10Â ma current.
#-Link-Snipped-#
A schematic illustration of resistive random access memory
For developing the Phase change memory, Wong and his colleagues chose materials like Tellurium, Germanium and Antimony. The memory cell in this case was found to be even more sensitive. A cell of 2.5 nm² area responded to a current of 1.4 µA changing its nature to amorphous state from its normal crystalline form. The amorphous form also having more resistance than its crystalline form.
Until now, designing silicon memory cells with sizes less than 16 nm was not feasible owing to the fact that there was always a chance of charge leakage or damaging nano memory cell. The team has come to conclusion of sandwiching the PCM material between bottom and top electrodes, making it more compact than the previous versions. The miniaturization would thus result in efficient and less power consuming memory cell. However, its durability is yet to be tested. Further research would make it more reliable after which we can see it replacing today's flash memory. The current work of scientists in this regard was presented in <em>2011 Symposium on VLSI technology, Kyoto</em>.
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