Nanowire 3D Transistors Set To Become More Compact

3D transistors are popular mainly because engineers can pack more of them onto a single chip as they are much more compact compared to the traditional transistors. But the amount of compactness will not be sufficient for ever. With changing trends, there is a need to shrink these 3D transistors further and one way to do it is to use vertical nanowires in the transistor design. Usually, the area taken up by a nanowire-based transistor is half of the area a planar transistor takes and it can be lesser if we consider more complicated components, like inverters.

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Xiang Li at the A*STAR Institute of Microelectronics and co-workers have now integrated two transistors onto a single vertical silicon nanowire, thus pushing the areal density limit of nanowire transistors even further. The team used wrap-around gates, or ‘gate-all-around’ gates, in the making of their device. These kinds of gates consist of a vertical cylinder, at the center of which lies the nanowire just as shown in the diagram. And what is better is that they are much better at controlling the transistor current than traditional planar gates.

Li and co-workers decreased the area required for a gate-all-around nanowire transistor by a factor of two as they constructed two transistors out of a single vertical nanowire. The two wrap-around gates are placed one above the other and are separated by a thin dielectric layer to isolate them electrically. Unlike other independent double-gate transistor designs, change of the gate voltage applied to one transistor does not change the threshold (or turn-on) voltage of the other. This basically implies that either of the gates can modulate the nanowire current independently.

As a result, the team was able to construct a simple logic device using just one nanowire. For instance, if a nanowire is doped with negative carriers, then current was able to flow when both gate voltages were high, but current stopped when either gate voltage was low. As it is obvious the device starts functioning like an AND circuit using half the area it would usually need. The stacked gate arrangement used here can also be of use in tunnel field effect transistor (TFET). Because TFETs rely on the tunneling of electrons across a barrier rather than the thermal activation of electrons, they turn on very quickly and hence will consume very little power. Li said that the tunnel junction required for a TFET could be formed between the two gates of the dual-gate nanowire geometry, allowing a particularly compact implementation. That is not the only possible application. It can also be put to use in other technologies, such as non-volatile memory.

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