Instruction cache memory VS data cache memory

Replies

• 

  rukawa

  Can somebody please answer me?
• 

  [Prototype]

  L1 cache for both Data and Instructions are of same size.
• 

  J Biswas

  CISC or RISC ??? Which you you need the answer for?
• 

  rukawa

  J Biswas

  CISC or RISC ??? Which you you need the answer for?

  RISC and CISC if possible
• 

  rukawa

  [Prototype]

  L1 cache for both Data and Instructions are of same size.

  Thanks for your answer
• 

  J Biswas

  In RISC DC blocks are nearly 8 to 16 times (or even) more than IC blocks. This helps in single cycle instructions. The Level1 register set, for DC is almost similar or sometimes more than IC blocks in CISC processors. Architecture in CISC chosen, governs.
  
  - JB -
• 

  rukawa

  J Biswas

  In RISC DC blocks are nearly 8 to 16 times (or even) more than IC blocks. This helps in single cycle instructions. The Level1 register set, for DC is almost similar or sometimes more than IC blocks in CISC processors. Architecture in CISC chosen, governs.
  
  - JB -

  Thank you. Do you know some articles or books which talk about cache performance?
• 

  J Biswas

  Not quite sure of market available text / design books dear, I never read any myself........we did L2 and L3 cache designs at Intel and AMD long time back. My knowledge is restricted only to a few processor families. I learnt from those company's architecture books.
  L1 register designs are controlled solely on the processor feature listing (speed, calc. capacity, opcode movements, machine cycle restrictions etc.) and usage. Different processors have different architectures.