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Edge Detection using VHDL/Verilog

Discussion in 'Electrical | Electronics | Communications' started by james david, Jan 7, 2008.

  1. james david

    james david Newbie

    Hello VLSI Design Engineers,
    We are a group of students doing M.S in VLSI Design. For one of our mini projects, we tried implementing Edge Detection algorithms for Sobel & Prewitt methods and were partially successful. However, for certain reference related to comparison with Canny algorithm, we require support for experts who would be glad to extend a hand.
    Is there any open core website with VHDL or Verilog codes of Sobel/Prewitt/Canny algorithms for implementation in FPGA. We would be glad if you could help us.
    Expressing our gratitude in advance. Thank You.
     
  2. DAVIDSOLOMON

    DAVIDSOLOMON Newbie

    hi sir

    as u said that about the edge detection using sobel operator in vhdl/veriloghdl

    can u send me the code .

    as i m in need for an paper to publish for my ph.d

    waiting for ur reply in apositive way with much anticipation

    regards

    david solomon raju
     
  3. ms_cs

    ms_cs Apprentice

    Engineering Discipline:
    Computer Science
    Edge detection algorithms are used in image processing mostly..I think....May I know the goal and features of this project?
     
  4. harsukh

    harsukh Newbie

    Hi
    can u please send me the vhdl code of sobel algorithm.i need it urgently.
    regards
    harsukh


     
  5. ajoy

    ajoy Newbie

    u can refer to cnblogs.com
     
  6. sauravgoswami

    sauravgoswami Rookie

    Engineering Discipline:
    Electrical & Electronics
    Hi james,why you need readymade codes??? if you have made proper flowchart,coding takes care of itself.anyhow can you tell were you gonna use this code???
     
  7. durga

    durga Star

    Engineering Discipline:
    Communications
    I guess this website might help you
    Edge Detection Tutorial
    www.altera.com

    also did you give a shot to mathworks.com?
     
  8. durga

    durga Star

    Engineering Discipline:
    Communications
    dude! you are publishing s PHD paper and waiting upon code?
     
    • Agree Agree x 1
  9. flukei

    flukei Newbie

    I am using Quartus II and you cant have more than always@(posedge/negedge)
    so i came up with a state machine edge detector
    it executes your code when at state s1 for negedge and s2 for posedge

    parameter
    s0=2'b00,
    s1=2'b01,
    s2=2'b10,
    s3=2'b11;

    reg [1:0] edge_det;

    case(edge_det)
    s0:
    begin
    if (in1==1)
    edge_det=s1;
    end
    s1://negedge
    begin
    if (in1==0)
    begin
    edge_det=s2;
    state<=in_state;
    end
    end
    s2://posedge
    begin
    if (in1==1)
    edge_det=s1;

    end
    s3:
    edge_det=s0;
    endcase

    //please tell me if this works
     
  10. flukei

    flukei Newbie

    please note:
    in1 is the net/signal you want to detect its transition
    the line with state<=in_state can be replaced with your code that should be executed at negedge
    if you want to execute your code at posedge add it after if(in1==1)
    and dont forget the line edge_det=s1;
     
  11. debu

    debu Apprentice

    Engineering Discipline:
    Computer Science
    @flukei: I may be wrong, but your code is simply checking for a high state or a low state in the in1 signal.

    If one needs to check the edge of a signal, one must use (in verilog):

    Code:
    module checkEdge (input signalIn);
    
        always @ (posedge signalIn)    //positive edge detection
        begin
            //do something
        end
    
        always @ (negedge signalIn)    //negative edge detection
        begin
            //do something
        end
      
        always @ (signalIn)    //any state change for "signalIn"
        begin
            //do something
        end
    
        always @ (*)    //any state change for any signal
        begin
           //do something
        end
    
    endmodule
    You can have any combinational logic in the last two, and any sequential logic in the first two.

    Hope this helps,

    Regards,

    Debu :)
     
  12. flukei

    flukei Newbie

    It is a state machine that replaces always@(posedge..) and always@(negedge..) verilog command,
    It checks if your values are going from high to low or low to high

    I used it to replace the always@() function because i got an error from altera's quartus II when i use more than one always@() function and it works
     
  13. debu

    debu Apprentice

    Engineering Discipline:
    Computer Science
    @flukei: Sorry my friend, It doesn't work. I'm using Xilinx ISE 10.1, with a Spartan 3A. In VHDL, to detect an edge one must use the block:
    Code:
    process (<signal>'event)
    Followed by the conditon to check for. The state machine that you provided will only check if the signal levels have changed since the previous state, and will not find an edge (the "event" in the "process" block will).

    The reason that you can use only one "always" block for the same condition in the same signal is the IEEE-1364 specifications.

    According to them, all statements within any block must be simultaneous, i.e, you can write any combination of sequential and combinational elements inside the same block, as long as they dont have any precedence in the circuit. So if there are two (or more) seperate and indipendent set of instructions that you need to execute everytime there is a condition then, you may write:

    Code:
    always (<signal condition>)
    begin
        <Statement set 1>
    
        <Statement set 2>
    
        <Statement set 3>
        ....
        ....
    end 
    //where statement sets 1,2,3... are non related 
    
    I hope I was clear in expressing my thoughts. (I often am not :) )

    Regards,

    Debu :)
     
  14. flukei

    flukei Newbie

    It worked on Altera's Quartus II
    and I was using verilog

    I guess my code couldnt be used for VHDL coding

    thank you for your feedback
     
  15. digitalpbk

    digitalpbk Newbie

  16. carla

    carla Newbie

    Hi
    can you send me your VHDL code of filter prewitt, i need it to implement it on FPGA and measure the energy
    thank you a lot
     
  17. elamparithi

    elamparithi Apprentice

    VHDL learning

    i feel hard tolearn vHDL/verilog can anybody suggest....these languages....:confused:
     
  18. nehk121

    nehk121 Newbie

    Re: Edge Detection using VHDL

    Hi
    can u please send me the vhdl code of sobel edge detection.i need it urgently.
    regards
     
  19. basavak16

    basavak16 Newbie

    Engineering Discipline:
    Aerospace
    sir,i am studying m.tech first sem and i was very much intersted in doing this as mini project so if you could send me code and its information it will be great helpful to me please dsend as early as possible
     
  20. vineet1992

    vineet1992 Newbie

    Engineering Discipline:
    Electronics & Communications
    sir, i want to simulate sobel edge detctor on Xilinux and modelsim using only VHDL.tell me how we can load image on xilinux and detect edges without using matlab or other software.

    is it possible?
    please suggest code and refrences.
    thanks.
     

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